Major Technology and Business Changes Sweeping Through the Semiconductor Industry
An industry veteran and technology leader Prith Banerjee, Chief Technology Officer at Ansys is effectively leading the advancing semiconductors industry, redefining strategy across the technology evolutions through simulation-based product innovation. Before joining Ansys, he has been in significant leadership roles across companies industry-wide. He spent the first 20 years in academia, as a professor at the University of Illinois and Northwestern University.
In a recent interaction with Indranil Chakraborty, Editor, siliconIndia, Dr. Prith gave a brief overview on the technology and business changes happening in Semiconductor Industry, and its impact on countries economic developments.
1.Can you elaborate on the Semiconductor industry scenario in India today amidst the global geopolitical crises?
Semiconductors have been crucial to various industries, such as aerospace and automobiles, for a long time. However, there has been a severe shortage of semiconductors in recent years. This shortage can be attributed to several factors, such as adverse effects on the supply chain due to COVID-19 and natural disasters, inflation, and the need for standard-setting to ensure interoperability. All major countries worldwide have increased their focus on building semiconductor supply chain self-sufficiency. However, this carries a risk of inward-looking supply chains and products potentially lacking interoperability.
India also recognises the importance of the electronics and semiconductor industry and has taken significant policy measures to develop in-house capabilities for design, development and testing. India is driving several initiatives such as the India Semiconductor Mission, National Policy on Electronics, Design Linked Incentive (DLI) & Production Linked Incentives (PLI) to become a global hub for Electronics System Design and Manufacturing (ESDM).
Further, the government has also announced plans to set up semiconductor manufacturing plants to make India more independent of geopolitical crises. Out-sourced assembly & test (OSAT), assembly, testing, marking, & packaging (ATMP) units, and display fab proposals have been received from multiple companies. Micron’s OSAT is the first approved plant in this area. There are at least five more proposals in the pipeline. The industry is willing to invest money and take advantage of the schemes that the government has rolled out.
2.In what way does the traditional chip design differ from the design of 3DIC systems?
There is a significant difference between 3D-IC system design and traditional chip design in terms of multiphysics effects and capacity. 3D-IC calls for vertically stacking multiple chips—called chiplets—in a single package or placing them next to each other on a silicon interposer connection substrate (2.5D-IC). This has many benefits, like the heterogeneous integration of different manufacturing technologies, including logic, memory, and analogue circuits in a more compact form factor. But it also raises novel design concerns because of the increased multiphysics interactions that traditional chip designers have not seen. Principal among these are thermal integrity, heat management, and electromagnetic signal integrity. Also, the gigantic scale of these integrated systems requires advanced hierarchical methods and cloud computing for ultra-high capacity.
3.How essential is ensuring the mechanical and thermal integrity of 3DICs for achieving overall system integrity, and why is it vital to address thermal concerns at different levels?
The proximity of chiplets stacked vertically and connected through micro bumps generates very high-power densities that can be difficult and expensive to cool effectively. Thermal concerns are the #1 limitation on achievable integration density in 2.5/3DIC systems. The differential thermal expansion introduced by temperature gradients and mismatches in CTE (coefficient of thermal expansion) between different components of the assembly lead to stress and warpage, which may cause failures such as micro bumps, shear and cracks. Designers must comprehend the thermal profile of each chiplet across every usage scenario and ensure controlled thermal distribution across the entire package.
This analysis must start early in the prototyping stage. If chiplets with hotspots that appear simultaneously are placed on top of each other, it can doom the design from the start. Excessive heat can cause thermal runaway or force the system to throttle back its clock speed and lose performance. Temperature is a critical factor in determining the robustness and durability of a product – and lower is better.
4.What are the key challenges in achieving system-level success?
In the contemporary semiconductor world, the chip design team is typically separate and distinct from the package design team. This conventional setup must evolve as 3D-IC technology blurs the lines between chip, package, and board. With logic blocks dispersed across multiple dice and vertically stacked chiplets interconnected through complex routing, the difference between package and die design becomes less clear.
This paradigm shift necessitates adaption in three crucial areas:
1.Cross-functional collaboration:Break the silos to foster collaboration between cross-functional and interdisciplinary teams. The cultural and organisational challenge lies in cultivating close-knit teams that simultaneously master board, package and silicon design.
2.Traditional EDA tools don’t support advanced design techniques for 3D-IC design. Open, flexible, extensible and high-capacity design platforms are essential for diverse challenges in 3D-IC system design.
3.Multiphysics analysis becomes imperative in 3D-IC design, considering concurrently the intricate interaction of various physics challenges. Thermal analysis is a primary concern throughout the design flow, given the significant impact of power dissipation. It can also lead to stress and warpage, strongly influenced by the system-level context, such as heatsinks and cooling fans.
In essence, the transformative nature of 3D-IC design requires semiconductor development teams to break the siloed organisational structure, adopt advanced design platforms and have a comprehensive understanding of multiphysics and multiscale challenges integrated into the design process to ensure system-level success for 3DIC design.
5.Can you speak about recent major supply chain-related challenges?
In 2022/2023, most people who booked cars had a waiting period of over nine months (for some models). OEMs were ready to deliver the cars without advanced features like automatic gear shift systems, ADAS systems, and advanced sensors because of a shortage of chips. This also impacted the manufacturing line of these OEMs; production went down, and as a result, tax collection went down, and economic growth slowed.
The geopolitical implications of this have not gone unnoticed, and governments worldwide, including India, have launched investment programs to ensure semiconductor supplies in the future, resulting in a surge in manufacturing capacity that will be coming online in the coming years.
What are the emerging trends and tech advancements in the semiconductor vertical?
•The growing trend toward bespoke silicon is a significant factor in the semiconductor landscape. As system houses like Microsoft and Amazon become increasingly dependent on semiconductor solutions for their business success, they have seen how customised semiconductor solutions have propelled industry leaders to the front of the pack. Off-the-shelf standard chips present a competitive disadvantage risk.
•Advanced packaging that includes 3D-IC, chiplets, D2D IPs, HBM
•AI chips are used to meet the requirements of artificial intelligence-specific applications. AI is notorious for requiring vast amounts of silicon computing power.
•Managing thermal, mechanical, and power challenges of these complex chip structures.
7.Can you touch upon Indigenous semiconductor manufacturing and its impact on the country's economic development?
•Semiconductor Complex Limited is the only foundry in India. This is a government-run foundry offering 180nm technology. There is a continuous discussion for upgrading this fab to a 45nm technology node, which would meet the semiconductor requirements for automotive parts.
•Private companies are also interested in setting up fabs in India. They see an untapped opportunity here. Today, every integrated circuit is imported into India. Often, these ICs are simple designs that can be designed and fabricated in India. The government’s focus is on Make In India and rolling out incentives. These companies are eager to evaluate this opportunity.
•Other than fabrication facilities, companies are discussing setting up electronics manufacturing services (EMS) lines, OSAT, and ATMP clean rooms. There are also discussions about setting up display fabs.
In a recent interaction with Indranil Chakraborty, Editor, siliconIndia, Dr. Prith gave a brief overview on the technology and business changes happening in Semiconductor Industry, and its impact on countries economic developments.
1.Can you elaborate on the Semiconductor industry scenario in India today amidst the global geopolitical crises?
Semiconductors have been crucial to various industries, such as aerospace and automobiles, for a long time. However, there has been a severe shortage of semiconductors in recent years. This shortage can be attributed to several factors, such as adverse effects on the supply chain due to COVID-19 and natural disasters, inflation, and the need for standard-setting to ensure interoperability. All major countries worldwide have increased their focus on building semiconductor supply chain self-sufficiency. However, this carries a risk of inward-looking supply chains and products potentially lacking interoperability.
India also recognises the importance of the electronics and semiconductor industry and has taken significant policy measures to develop in-house capabilities for design, development and testing. India is driving several initiatives such as the India Semiconductor Mission, National Policy on Electronics, Design Linked Incentive (DLI) & Production Linked Incentives (PLI) to become a global hub for Electronics System Design and Manufacturing (ESDM).
Further, the government has also announced plans to set up semiconductor manufacturing plants to make India more independent of geopolitical crises. Out-sourced assembly & test (OSAT), assembly, testing, marking, & packaging (ATMP) units, and display fab proposals have been received from multiple companies. Micron’s OSAT is the first approved plant in this area. There are at least five more proposals in the pipeline. The industry is willing to invest money and take advantage of the schemes that the government has rolled out.
2.In what way does the traditional chip design differ from the design of 3DIC systems?
There is a significant difference between 3D-IC system design and traditional chip design in terms of multiphysics effects and capacity. 3D-IC calls for vertically stacking multiple chips—called chiplets—in a single package or placing them next to each other on a silicon interposer connection substrate (2.5D-IC). This has many benefits, like the heterogeneous integration of different manufacturing technologies, including logic, memory, and analogue circuits in a more compact form factor. But it also raises novel design concerns because of the increased multiphysics interactions that traditional chip designers have not seen. Principal among these are thermal integrity, heat management, and electromagnetic signal integrity. Also, the gigantic scale of these integrated systems requires advanced hierarchical methods and cloud computing for ultra-high capacity.
3.How essential is ensuring the mechanical and thermal integrity of 3DICs for achieving overall system integrity, and why is it vital to address thermal concerns at different levels?
The proximity of chiplets stacked vertically and connected through micro bumps generates very high-power densities that can be difficult and expensive to cool effectively. Thermal concerns are the #1 limitation on achievable integration density in 2.5/3DIC systems. The differential thermal expansion introduced by temperature gradients and mismatches in CTE (coefficient of thermal expansion) between different components of the assembly lead to stress and warpage, which may cause failures such as micro bumps, shear and cracks. Designers must comprehend the thermal profile of each chiplet across every usage scenario and ensure controlled thermal distribution across the entire package.
This analysis must start early in the prototyping stage. If chiplets with hotspots that appear simultaneously are placed on top of each other, it can doom the design from the start. Excessive heat can cause thermal runaway or force the system to throttle back its clock speed and lose performance. Temperature is a critical factor in determining the robustness and durability of a product – and lower is better.
4.What are the key challenges in achieving system-level success?
In the contemporary semiconductor world, the chip design team is typically separate and distinct from the package design team. This conventional setup must evolve as 3D-IC technology blurs the lines between chip, package, and board. With logic blocks dispersed across multiple dice and vertically stacked chiplets interconnected through complex routing, the difference between package and die design becomes less clear.
India is driving several initiatives such as the India Semiconductor Mission, National Policy on Electronics, Design Linked Incentive (DLI) & Production Linked Incentives (PLI) to become a global hub for Electronics System Design & Manufacturing (ESDM)
This paradigm shift necessitates adaption in three crucial areas:
1.Cross-functional collaboration:Break the silos to foster collaboration between cross-functional and interdisciplinary teams. The cultural and organisational challenge lies in cultivating close-knit teams that simultaneously master board, package and silicon design.
2.Traditional EDA tools don’t support advanced design techniques for 3D-IC design. Open, flexible, extensible and high-capacity design platforms are essential for diverse challenges in 3D-IC system design.
3.Multiphysics analysis becomes imperative in 3D-IC design, considering concurrently the intricate interaction of various physics challenges. Thermal analysis is a primary concern throughout the design flow, given the significant impact of power dissipation. It can also lead to stress and warpage, strongly influenced by the system-level context, such as heatsinks and cooling fans.
In essence, the transformative nature of 3D-IC design requires semiconductor development teams to break the siloed organisational structure, adopt advanced design platforms and have a comprehensive understanding of multiphysics and multiscale challenges integrated into the design process to ensure system-level success for 3DIC design.
5.Can you speak about recent major supply chain-related challenges?
In 2022/2023, most people who booked cars had a waiting period of over nine months (for some models). OEMs were ready to deliver the cars without advanced features like automatic gear shift systems, ADAS systems, and advanced sensors because of a shortage of chips. This also impacted the manufacturing line of these OEMs; production went down, and as a result, tax collection went down, and economic growth slowed.
The geopolitical implications of this have not gone unnoticed, and governments worldwide, including India, have launched investment programs to ensure semiconductor supplies in the future, resulting in a surge in manufacturing capacity that will be coming online in the coming years.
What are the emerging trends and tech advancements in the semiconductor vertical?
•The growing trend toward bespoke silicon is a significant factor in the semiconductor landscape. As system houses like Microsoft and Amazon become increasingly dependent on semiconductor solutions for their business success, they have seen how customised semiconductor solutions have propelled industry leaders to the front of the pack. Off-the-shelf standard chips present a competitive disadvantage risk.
•Advanced packaging that includes 3D-IC, chiplets, D2D IPs, HBM
•AI chips are used to meet the requirements of artificial intelligence-specific applications. AI is notorious for requiring vast amounts of silicon computing power.
•Managing thermal, mechanical, and power challenges of these complex chip structures.
7.Can you touch upon Indigenous semiconductor manufacturing and its impact on the country's economic development?
•Semiconductor Complex Limited is the only foundry in India. This is a government-run foundry offering 180nm technology. There is a continuous discussion for upgrading this fab to a 45nm technology node, which would meet the semiconductor requirements for automotive parts.
•Private companies are also interested in setting up fabs in India. They see an untapped opportunity here. Today, every integrated circuit is imported into India. Often, these ICs are simple designs that can be designed and fabricated in India. The government’s focus is on Make In India and rolling out incentives. These companies are eager to evaluate this opportunity.
•Other than fabrication facilities, companies are discussing setting up electronics manufacturing services (EMS) lines, OSAT, and ATMP clean rooms. There are also discussions about setting up display fabs.
